--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   23:12:41 10/10/2013
-- Design Name:   
-- Module Name:   C:/Users/Ling Chun Kai/Documents/NUS modules/CG3207/Lab/CG3207/shift_test.vhd
-- Project Name:  LAB2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: shifter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY shift_test IS
END shift_test;
 
ARCHITECTURE behavior OF shift_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT shifter
    PORT(
         OP : IN  std_logic_vector(1 downto 0);
         A : IN  std_logic_vector(31 downto 0);
         B : IN  std_logic_vector(31 downto 0);
         C : OUT  std_logic_vector(31 downto 0);
         overflow_flag : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal OP : std_logic_vector(1 downto 0) := (others => '0');
   signal A : std_logic_vector(31 downto 0) := (others => '0');
   signal B : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal C : std_logic_vector(31 downto 0);
   signal overflow_flag : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: shifter PORT MAP (
          OP => OP,
          A => A,
          B => B,
          C => C,
          overflow_flag => overflow_flag
        );
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		
		OP <= "01"; -- shift left logical
      -- insert stimulus here 
		A <= "11000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001000";
		B <= "00000000000000000000000000000011";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001001";
		B <= "00000000000000000000000000011111";
		
		wait for 50 ns;
		
		OP <= "10"; -- shift right arithematic
      -- insert stimulus here 
		A <= "11000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001001";
		B <= "00000000000000000000000000000011";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "11000010001000000001000000001001";
		B <= "00000000000000000000000000011111";
		
		wait for 50 ns;
		
		A <= x"12345676";
		B <= x"00000005";
		
		wait for 50 ns;
		
		OP <= "11"; -- shift right logical
      -- insert stimulus here 
		A <= "11000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001000";
		B <= "00000000000000000000000000000011";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001000";
		B <= "00000000000000000000000000000001";
		
		wait for 50 ns;
		
		A <= "01000010001000000001000000001001";
		B <= "00000000000000000000000000011111";
		
		wait for 50 ns;
		
		
      wait;
   end process;

END;
